Source-to-Source Instrumentation for the Optimization of an Automatic Reading System

Recording address traces that occur during a program execution is a significant technique for computer performance analysis. This paper describes a software method for address tracing via the instrumentation of C based languages. All program transformations are performed at the language level. This approach, which differs from the usual methods, allows portable and flexible program instrumentation. This tool has been developed to make easier the memory optimization of LIREChèques, an automatic bank check reading system. Two applications of the tool are clearly identified: (i) data cache use optimization, (ii) dynamic memory use optimization.     

一种低延迟低功耗的片上全局互连方法

提出了一种用于片上全局互连的混合插入方法. 该方法利用中继驱动器和低摆幅差分信号电路在驱动不同长度连线时的优点，将它们混合插入到连线的合适位置，从而降低互连的延时和功耗. 模拟结果表明，该方法与已有方法相比在延时、能耗、能耗延时积以及面积等方面都获得了一定程度的改善.     

An efficient location cache scheme for three‐level database architecture in PCS networks

Recently, hierarchical architecture for location databases has been proposed in order to accommodate the growing number of personal communication systems users. With the three‐level hierarchical database architecture, which is compatible with the current cellular mobile systems, newly developed additional databases, including the regional location database (RLR), are positioned between the HLR and the VLRs. We propose an efficient cache scheme, the double T‐thresholds location cache scheme, which could reduce the network and database costs to lookup a portable using the three‐level architecture. This scheme extends the existing T‐threshold location cache scheme, which is effective only under the two‐level architecture of location databases currently adopted by IS‐41 and GSM. The idea behind our proposed scheme is to use two pieces of cache information, VLR and RLR, which serve the called portables. These two pieces are required in order to exploit not only the locality of a registration area (RA), but also the locality of a regional registration area (RRA), a wide area covered by the RLR. We also use two threshold values in order to determine whether the two pieces are obsolete. In order to model the RRA residence time, the branching Erlang‐∞ distribution is introduced. The cost analysis presented in this paper shows that the double T‐thresholds location cache scheme significantly reduces the network and database costs for most patterns of portables. Copyright © 2001 John Wiley & Sons, Ltd.     

基于QPSO的震动传感器片上相位补偿器设计方法

震动传感器的系统相位非一致性会对地震波到时时差提取产生很大的误差,严重影响震源定位精度;针对这一问题,提出了一种基于量子粒子群优化算法（QPSO）的震动传感器片上相位补偿器设计方法。首先对震动传感器进行相位标定,获得传感器与参考传感器的相位差;其次设计基于QPSO算法的相位补偿滤波器对相位差进行修正,使其无限趋近于0;最后,将相位补偿滤波器封装成FPGA软核部署于FPGA上,完成对震动传感器的相位片上实时补偿。为了验证该方法的性能,将相位补偿滤波器部署于自研的多通道震动信号采集系统上,对8个相同型号震动传感器进行相位一致性校准。试验结果表明,在震动传感器频响范围内,该方法可以将2.5°内的传感器相位差实时修正至0.0044°以下,实现了震动传感器阵列的相位一致性实时校准。该成果在地下浅层震源定位领域具有较强的应用价值。     

Enhancing MC68030 performance using the SN74ACT2155 cache

Texas Instruments highlights the important questions facing the system designer who needs to interface a cache to a fast microprocessor, giving an example solution using its cache chip     

电视墙系统中的存储器设计

电视墙系统中的存储器设计有多种方案。本文通过比较优选了其中的一种,即一■存储器方案,并详细介绍了具体电路。     

并行文件系统中Disk Cache一致性协议及其性能分析

本文在并行文件系统中引入ｄｉｓｋｃａｃｈｅ多复本技术，从而为并行计算机提供高性能的文件系统．对于ｄｉｓｋｃａｃｈｅ多复本间数据一致性维护，本文提出了“主从式”和“对称式”两类方法，并从其应用的通用性角度，基于等概率模型，对各类方法以及ｄｉｓｋｃａｃｈｅ单复本系统进行了性能分析和比较．     

标准数字CMOS工艺中LC谐振回路的改进和应用

提出了一种在标准数字CMOS工艺条件下,提高片上螺旋电感性能的实用方法,以及在缺少双层多晶硅电容的情况下,可以大大节约芯片面积的一种电容实现方法.介绍了这两种方法在电路设计中的一种应用,即利用0 .35 μm1P4 M标准数字CMOS工艺实现的、单片集成的L C压控振荡器.     

Area Analysis for On-chip Routers with Different Data-link Widths

Compared with the traditional and inter-chip networks, on-chip networks （NoCs） have enormous wire resources which can be traded for improving other performance requirements. This means that much wider data links can be used for NoCs. This paper focuses on the area costs for on-chip routers under four different data-link widths： 8 bits, 16 bits, 128 bits, and 256bits. Firstly, a virtual-channel based on-chip router is introduced. Secondly, the components of the router are implemented by Verilog HDL models and synthesized by Quartus II 4.0 in a FPGA device. Finally, the area costs are analyzed. It can be seen from the results that data-link width has great influence on area costs of buffers and crossbar while has no influence on area costs of arbiter.